1. Field of the Invention
The present invention is in the field of chemical vapor reactors. More particularly, the present invention is in the field of plasma enhanced chemical vapor deposition and plasma etching.
2. Related Technology
A conventional and exemplary plasma enhanced chemical vapor deposition (PECVD) apparatus and method is shown in accord with U.S. Pat. No. 4,827,870, issued 9 May 1989, to James C. Lee. According to the teaching of Lee, a precision multilayer optical interference coating is deposited on an optical substrate having a complex topology. In order to achieve the deposition of precision multi-layer coatings, the Lee patent discloses the use of a feed electrode which is complimentary in shape to a cavity formed in a passive or ground electrode. The ground electrode is in turn shaped to hold and generally to match the shape of the substrate. For example, a substrate may have the shape of a visor for an aviator's helmet. Accordingly, the ground electrode would form a cavity formed to accommodate the shape of the visor, and the feed electrode would be shaped to be complementary to the shape of the substrate topology, and generally complementary to the cavity shape of the ground electrode.
Another conventional form of plasma enhanced chemical vapor deposition apparatus and method is shown in U.S. Pat. No. 5,009,920, issued 23 Apr. 1991, also to James C. Lee. This latter patent to Mr. Lee addresses the plasma enhanced chemical vapor deposition of precise multi-layer coatings to optical and other substrates, such as mirrors for ring laser gyroscopes. Similarly to the '870 patent discussed above, the '920 patent discloses the use of a passive or ground-potential electrode and an active or feed electrode having shapes which are generally complimentary to one another. The active and passive electrodes also accommodate and compliment the topology of a substrate placed into a gap defined between the electrodes.
Neither of these conventional PECVD apparatus, however, are believed to address problems of non-uniformity in the thickness of deposited coatings across their dimensions of length and width, as typically results from such conventional plasma enhanced chemical vapor deposition processes. In the fabrication of integrated circuits on processing wafers of semiconductor material, such as silicon, plasma enhanced chemical vapor deposition is frequently used to apply successive layers of material on the substrate of the processing wafers. The processing wafers of substrate material are typically about three inches, about six inches, or about eight inches in diameter, for example, and have planar opposite faces.
In a batch type of wafer processing method, the processing wafers move from one work station to the next within a single reaction chamber having plural work stations. At each work station, a portion of the total thickness of a particular material to be deposited using the plasma enhanced chemical vapor deposition process is applied. That is, each work station in the batch processing reaction chamber applies a respective sub-layer of material, and the successive sub-layers aggregate to form a single material layer in the morphology of the integrated circuit. Alternatively, a plurality of separate plasma enhanced chemical vapor deposition reaction chambers, known as "cluster tools", may be used individually to build up the sub-layers of material necessary for a particular layer of the integrated circuit morphology. In this case, the processing wafers move from one reaction chamber to the next to have the successive sub-layers applied.
However, regardless of whether the successive sub-layers of material are applied to semiconductor integrated circuit processing wafers using a single batch-processing reaction chamber, or by using cluster tools to apply the successive sub-layers, it has been found that the PECVD process sometimes results in a non-uniformity in the thickness of successive sub-layers across the dimensions of a wafer. Generally this non-uniform thickness appears across a diameter of the round processing wafers, and is referred to as a "bull's eye" effect. That is, the individual sub-layers are typically thicker in the center of the processing wafer, and thinner at the wafer perimeter, or vice versa.
The non-uniformity of deposited sub-layer thickness sometimes encountered in PECVD processing of semiconductor wafers is believed to be related to a variety of processing parameters including the particulars of the material being deposited, the temperature and pressure of processing, the gas flow direction at particular locations in the gap between the active electrode and the substrate, and the concentration of active feed gas in the gap at particular locations of the plasma. However, non-uniformities in sub-layer thickness non-uniformities conventionally can not be brought down to less than a certain level because of the need to control other aspects of the material deposition process. Although some of the sub-layers may have opposite or compensating non-uniformities in their thicknesses, if several of the sub-layers in a particular material layer are non-uniform in their thickness in the same way, and insufficient compensating non-uniformities are present in the other sub-layers on the processing wafer, then the processing wafer with the finished material layer will have a problematic thickening at its center or at its edges. Such a thickening at the center or edges of a semiconductor integrated circuit processing wafer may be detrimental to subsequent processes in the fabrication of the integrated circuits on the wafer, and is an uncontrolled variable in the manufacturing process.
Alternatively, plasma reaction chambers may also be used to effect etching of a particular area of a material layer on an integrated circuit processing wafer. This etching operation is known in the art of manufacturing integrated circuits. Generally, a gas such as a mixture of Freons, and possibly including Argon (CHF.sub.2, CF.sub.4, and possibly with added Argon) is employed, which in the plasma reaction produces radicals CF.sub.2, and CF.sub.3. These radicals etch an oxide surface layer on the integrated circuit processing wafer. In this instance also, a bull's eye effect is experienced. That is, the rate of material removal by etching is non-uniform across the diameter of a processing wafer, so that the thickness of the material layer remaining after the etching operation is non-uniform across its diameter even if it was uniform before the etching operation.
It can be seen in view of the above, that a great variability exists in the manufacture of integrated circuits using plasma reactors. The material layers deposited with such reactors in a PECVD process may be non-uniform across a dimension of the wafers, and the non-uniformity may be such that the material layer is center-thick, or center-thin (convex or concave). Also, the etching process carried out in plasma reactors may have a non-uniformity of material etching so that the remaining layer of material after the etching operation is similarly non-uniform across a dimension of the processing wafer. This post-etching material layer may also be center-thick or center-thin (convex or concave).
Because of the many steps of material deposition, masking, and etching which are necessary to build up the morphology of current complex integrated circuits, the variations of material thickness across a dimension of an integrated circuit processing wafer can cause great difficulties in the manufacturing environment, and reduced yields from this manufacturing. These non-uniformities of material thickness typically result from the non-uniformity effects in both PECVD and plasma reaction etching. As mentioned, current integrated circuit processing wafers have grown in diameter from the historical three inch size to current six inch and eight inch wafers. Additionally, even larger integrated circuit processing wafers of up to twelve inches, or larger, in diameter are being considered for use in manufacturing integrated circuits. Consequently, the problems associated with thickness non-uniformities of deposited and etched material layers are expected to be more troublesome as the size of the processing wafers increases.